general description the max5075 is a +4.5v to +15v push-pull, current-fed topology driver subsystem with an integrated oscillator for use in telecom module power supplies. the device drives two mosfets connected to a center-tapped transformer primary providing secondary-side, isolated, negative or positive voltages. this device features a pro- grammable, accurate, integrated oscillator with a syn- chronizing clock output that synchronizes an external pwm regulator. a single external resistor programs the internal oscillator frequency from 50khz to 1.5mhz. the max5075 incorporates a dual mosfet driver with ?a peak drive currents and 50% duty cycle. the mosfet driver generates complementary signals to drive external ground-referenced n-channel mosfets. the max5075 is available with a clock output frequency to mosfet driver frequency ratio of 1x, 2x, and 4x. the max5075 is available in a thermally enhanced 8-pin ?ax package and is specified over the -40? to +125? operating temperature range. applications current-fed, high-efficiency power-supply modules power-supply building subsystems push-pull driver subsystems features ? current-fed, push-pull driver subsystem ? programmable, accurate internal oscillator ? single +4.5v to +15v supply voltage range ? dual 3a gate-drive outputs ? 1ma operating current at 250khz with no capacitive load ? synchronizing clock frequency generation options ? thermally enhanced 8-pin max package ? -40c to +125c operating temperature range max5075 push-pull fet driver with integrated oscillator and clock output ________________________________________________________________ maxim integrated products 1 ordering information 19-3662; rev 1; 5/07 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration appears at end of data sheet. part pin- package top mark pkg code f clk /f ndrv_ ratio max5075aaua 8 ?ax-ep* aaau u8e-2 1 max5075baua 8 ?ax-ep* aaav u8e-2 2 max5075caua 8 ?ax-ep* aaaw u8e-2 4 * ep = exposed paddle. note: all devices specified for -40? to +125? operating temperature range. max5075 1nf 4.7k ? ndrv2 drvh drvl gnd gnd v in v in pwm controller syncin ndrv1 v cc rt pgnd i.c. clk v cc v out typical operating circuit ?ax is a registered trademark of maxim integrated products, inc.
max5075 push-pull fet driver with integrated oscillator and clock output 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = +12v, r rt = 124k ? , ndrv1 = ndrv2 = open, t a = t j = -40? to +125?, unless otherwise noted. typical values are measured at t a = +25 c.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to dgnd, pgnd .............................................-0.3v to +18v clk, rt to dgnd.....................................................-0.3v to +6v ndrv1, ndrv2 to pgnd...........................-0.3v to (v cc + 0.3v) dgnd to pgnd.....................................................-0.3v to +0.3v clk current......................................................................?0ma ndrv1, ndrv2 peak current (200ns) ..................................?a ndrv1, ndrv2 reverse current (latchup current)...... 500ma continuous power dissipation (t a = +70 c) 8-pin ?ax (derate 10.3mw/ c above +70 c) ...........825mw operating temperature range .........................-40 c to +125 c maximum junction temperature .....................................+150 c storage temperature range .............................-60 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units supply input voltage supply range v cc 4.5 15.0 v switching supply current i ccsw f osc = 250khz 1 3 ma undervoltage lockout v uvlo v cc rising 3 3.5 4 v uvlo hysteresis 300 mv oscillator frequency range f osc (note 2) 50 1500 khz accuracy f osc = 250khz , 6v v cc 15v (note 3) -8 +10 % oscillator jitter ?.6 % 7v v cc 15v 3.9 5.0 clk output high voltage i clk = 1ma 4.5v v cc 7v 3.35 5.0 v clk output low voltage i clk = -1ma 50 mv clk output rise time c clk = 30pf 35 ns clk output fall time c clk = 30pf 10 ns gate drivers (ndrv1, ndrv2) output high voltage v oh i ndrv1 = i ndrv2 = 100ma v cc - 0.3 v output low voltage v ol i ndrv1 = i ndrv2 = -100ma 0.3 v output peak current i p sourcing and sinking 3 a ndrv_ sourcing 100ma 1.8 3 driver output impedance ndrv_ sinking 100ma 1.6 2.6 ? latchup current protection reverse current at ndrv1/ndrv2 400 ma rise time t r c load = 2nf 10 ns fall time t f c load = 2nf 10 ns note 1: the max5075 is 100% tested at t a = t j = +125 c. all limits over temperature are guaranteed by design. note 2: use the following formula to calculate the max5075 oscillator frequency: f osc = 10 12 /(32 x r rt ). note 3: the accuracy of the oscillator? frequency is lower at frequencies greater than 1mhz.
max5075 push-pull fet driver with integrated oscillator and clock output _______________________________________________________________________________________ 3 typical operating characteristics (v cc = +12v, r rt = 124k ? , ndrv_ = open, clk = open.) supply current vs. supply voltage max5075 toc01 supply voltage (v) supply current (ma) 14 13 12 11 10 9 8 7 6 5 1 2 3 4 5 6 7 0 415 f osc = 1.25mhz f osc = 500khz f osc = 250khz f osc = 100khz f osc = 50khz supply current vs. c clk max5075 toc02 c clk (pf) supply current (ma) 80 60 40 20 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.00 0100 r rt = 124k ? temperature ( c) 100 75 25 50 0 -25 -50 125 supply current vs. temperature max5075 toc03 supply current (ma) 1.02 1.04 1.06 1.08 1.10 1.12 1.14 1.16 1.18 1.20 1.00 f osc = 250khz clk rise time vs. supply voltage max5075 toc04 supply voltage (v) clk rise time (ns) 14 13 11 12 6 7 8 9 10 5 5 10 15 20 25 30 35 40 45 50 0 415 c clk = 30pf clk rise time vs. temperature max5075 toc05 temperature ( c) clk rise time (ns) 100 75 50 25 0 -25 37.0 37.5 38.0 38.5 39.0 39.5 36.5 -50 125 c clk = 30pf 2 4 6 8 10 12 14 0 clk fall time vs. supply voltage max5075 toc06 supply voltage (v) clk fall time (ns) 14 13 11 12 678910 5 415 c clk = 30pf clk fall time vs. temperature max5075 toc07 temperature ( c) clk fall time (ns) 100 75 50 25 0 -25 2 4 6 8 10 12 0 -50 125 c clk = 30pf oscillator frequency (khz) 244 246 248 250 252 254 256 242 oscillator frequency vs. supply voltage max5075 toc08 supply voltage (v) 14 13 11 12 678910 5 415 r rt = 124k ? t a = -40 c t a = +25 c t a = +125 c
max5075 push-pull fet driver with integrated oscillator and clock output 4 _______________________________________________________________________________________ typical operating characteristics (continued) (v cc = +12v, r rt = 124k ? , ndrv_ = open, clk = open.) oscillator frequency vs. r rt max5075 toc09 r rt (k ? ) oscillator frequency (khz) 100 100 1000 10,000 10 10 1000 ndrv frequency vs. clk frequency max5075 toc10 clk frequency (khz) ndrv frequency (khz) 1250 1000 250 500 750 100 200 300 400 500 600 700 800 0 0 1500 max5075a max5075b max5075c max5075a waveform max5075 toc11 2 s/div ndrv1 5v/div ndrv2 5v/div clk 5v/div r rt = 124k ? max5075b waveform max5075 toc12 2 s/div ndrv1 5v/div ndrv2 5v/div clk 5v/div r rt = 124k ? max5075c waveform max5075 toc13 4 s/div ndrv1 5v/div ndrv2 5v/div clk 5v/div r rt = 124k ?
max5075 push-pull fet driver with integrated oscillator and clock output _______________________________________________________________________________________ 5 pin description pin name function 1 clk synchronizing clock output. clock output with a 10ma peak current drive that can be used to synchronize an external pwm regulator. clk/ndrv1 frequency has a 1x, 2x, or 4x ratio. see the synchronizing clock output section. 2 i.c. internal connection. connect to ground. internal function. 3rt oscillator timing resistor connection. bypass rt with a series combination of a 4.7k ? resistor and a 1nf capacitor to dgnd. connect a resistor from rt to dgnd to set the internal oscillator. 4 dgnd digital ground. connect dgnd to ground plane. 5 pgnd power ground. connect pgnd to ground plane. 6 ndrv1 gate driver 1. connect ndrv1 to the gate of the external n-channel fet. 7 ndrv2 gate driver 2. connect ndrv2 to the gate of the external n-channel fet. 8v cc power-supply input. bypass v cc to pgnd with 0.1? || 1? ceramic capacitors. ep ep exposed pad. internally connected to dgnd. connect exposed pad to ground plane. ndrv1 pgnd v cc ndrv2 t-ff uvlo 3.5v q q clk rt dgnd osc i.c. 5v ldo v cc a (1x) b (2x) c (4x) max5075 q q q q internal function figure 1. max5075 functional diagram
max5075 detailed description the max5075 is a +4.5v to +15v push-pull, current-fed topology driver subsystem with an integrated oscillator for use in 48v module power supplies. the max5075 features a programmable, accurate inte- grated oscillator with a synchronizing clock output that can be used to synchronize an external pwm stage. a single external resistor programs the internal oscillator frequency from 50khz to 1.5mhz. the max5075 incorporates a dual mosfet driver with ?a peak drive currents and a 50% duty cycle. the mosfet driver generates complementary signals to drive external ground-referenced n-channel mosfets. the max5075 is available with a clock output frequency to mosfet driver frequency ratios of 1x , 2x, and 4x. internal oscillator an external resistor at rt programs the max5075 internal oscillator frequency from 50khz to 1.5mhz. the max5075a/b ndrv1 and ndrv2 switching frequen- cies are one-half the programmed oscillator frequency with a nominal 50% duty cycle. the max5075c ndrv1 and ndrv2 switching frequencies are one-fourth the oscillator frequency. use the following formula to calculate the internal oscil- lator frequency: where f osc is the oscillator frequency and r rt is a resistor connected from rt to dgnd in ohms. place a series combination of a 4.7k ? resistor and a 1nf capacitor from rt to dgnd for stability and to filter out noise. synchronizing clock output the max5075 provides a buffered clock output that can be used to synchronize the oscillator input of a pwm con- troller. clk is powered from an internal 5v regulator and sources/sinks up to 10ma. the max5075 has internal clk output frequency to ndrv1 and ndrv2 switching frequency ratios set to 1x, 2x, or 4x (table 1). the max5075a has a clk frequency to ndrv_ frequen- cy ratio set to 1x. the max5075b has a clk frequency to ndrv_ frequency ratio set to 2x and the max5075c has a clk frequency to ndrv_ frequency ratio set to 4x. there is a typical 30ns delay from clk to ndrv_ output. applications information supply bypassing pay careful attention to bypassing and grounding the max5075. peak supply and output currents may exceed 3a when driving large mosfets. ground shifts due to insufficient device grounding may also disturb other cir- cuits sharing the same ground-return path. any series inductance in the v cc , ndrv1, ndrv2, and/or gnd paths can cause noise due to the very high di/dt when switching the max5075 with any capacitive load. place one or more 0.1? ceramic capacitors in parallel as close to the device as possible to bypass v cc to pgnd. use a ground plane to minimize ground-return resistance and inductance. place the external mosfets as close as possible to the max5075 to further minimize board induc- tance and ac path impedance. f xr osc rt = 10 32 12 push-pull fet driver with integrated oscillator and clock output 6 _______________________________________________________________________________________ part f clk f ndrv1 f clk to f sw ratio max5075a f osc / 2 f osc / 2 1 max5075b f osc f osc / 2 2 max5075c f osc f osc / 4 4 table 1. max5075 clk output frequency clk osc ndrv1 ndrv2 clk osc ndrv1 ndrv2 clk osc ndrv1 ndrv2 max5075a max5075b max5075c figure 2. max5075 clk timing diagrams
power dissipation the power dissipation of the max5075 is a function of the sum of the quiescent current and the output current (either capacitive or resistive load). maintain the sum of the currents so the maximum power dissipation limit is not exceeded. the power dissipation (p diss ) due to the quiescent switching supply current (i ccsw ) can be cal- culated as: p diss = v cc x i ccsw for capacitive loads, use the following equation to esti- mate the power dissipation: p load = 2 x c load x v cc 2 x f ndrv_ where c load is the capacitive load at ndrv1 and ndrv2, v cc is the supply voltage, and f ndrv_ is the max5075 ndrv_ switching frequency. calculate the total power dissipation (p t ) as follows: p t = p diss + p load layout recommendations the max5075 sources and sinks large currents that can create very fast rise and fall edges at the gate of the switching mosfets. the high di/dt can cause unaccept- able ringing if the trace lengths and impedances are not well controlled. use the following pc board layout guide- lines when designing with the max5075: place one or more 0.1? decoupling ceramic capacitors from v cc to pgnd as close to the device as possible. connect v cc and all ground pins to large copper areas. place one bulk capaci- tor of 10? on the pc board with a low-impedance path to the v cc input and pgnd of the max5075. two ac current loops form between the device and the gate of the driven mosfets. the mosfets look like a large capacitance from gate to source when the gate pulls low. the current loop is from the mosfet gate to ndrv1 and ndrv2 of the max5075, to pgnd, and to the source of the mosfet. when the gate of the mosfet pulls high, the current is from the v cc terminal of the decou- pling capacitor, to v cc of the max5075, to ndrv1 and ndrv2, and to the mosfet gate and source. both charging current and discharging current loops are important. minimize the physical distance and the impedance in these ac current paths. keep the device as close to the mosfet as possible. chip information transistor count: 1335 process: bicmos max5075 push-pull fet driver with integrated oscillator and clock output _______________________________________________________________________________________ 7 1 2 3 4 8 7 6 5 v cc ndrv2 ndrv1 pgnd dgnd rt i.c. clk *ep *exposed paddle connected to dgnd. max5075 max top view pin configuration
max5075 push-pull fet driver with integrated oscillator and clock output maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 8l, max, exp pad.eps c 1 1 21-0107 revision history pages changed at rev 1: 1, 2, 5, 6, 8
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